An inverter layout technique for propagation delay minimization

Through various cases of inverter layout, the change in the propagation delay time (tPD) in the ring oscillator that consists of inverters can be analyzed. In this paper, an inverter layout technique for tPD minimization is presented. Through the case-by-case layout, to reduce the tPD, we propose that layout engineers should reduce the input and output node length. The proposed technique post-simulated in a 0.18um CMOS process achieves maximum 7.318% reduced tPD compared to the basic inverter layout.