Face Recognition HW/SW IP implementation and validation for high reliability using a Virtual Platform

This paper presents design details of a Virtual Platform (VP) which is used for developing real time hardwired face recognition system. VP is promising technology to develop complex HW/SW system because it enables the simultaneous development of hardware and software. We have implemented a Virtual Platform and we used it for developing FPGA based face recognition system. The hardware portion is modeled with Transaction Level Model (TLM) in early phase of development. After hardware have been implemented, TLM model is substituted with real hardware system. The software is simultaneously developed with TLM hardware model and SW/HW integrity verification is seamlessly done by substituting TLM model with FPGA based real hardware. TLM model was efficient because it was much faster than RTL model and it can be seamlessly interfaced with SW development environment of virtual platform. FPGA based face recognition system was fully verified using application software running on virtual platform.