• DocumentCode
    73145
  • Title

    An Effective Approach of Reducing the Keep-Out-Zone Induced by Coaxial Through-Silicon-Via

  • Author

    Fengjuan Wang ; Zhangming Zhu ; Yintang Yang ; Xiangkun Yin ; Xiaoxian Liu ; Ruixue Ding

  • Author_Institution
    Sch. of Microelectron., Xidian Univ., Xi´an, China
  • Volume
    61
  • Issue
    8
  • fYear
    2014
  • fDate
    Aug. 2014
  • Firstpage
    2928
  • Lastpage
    2934
  • Abstract
    Keep-out-zone (KOZ) is a conservative way to prevent any devices/cells from being impacted by the through-silicon via (TSV)-induced stress. In this paper, an effective approach was proposed of reducing the KOZ induced by coaxial TSV, by using the structure of coaxial-annular TSV, without decreasing the electrical performance of coaxial TSV. The analytical model was developed appropriate for the thermal stress induced by both coaxial and coaxial-annular TSVs, and was verified by the finite element method. The KOZs induced by coaxial and coaxial-annular TSVs were compared in detail, and the effects of Cu plasticity, TSV material, TSV size, and inner metal plating ratio of coaxial-annular TSV were also studied. The electrical characteristics of different TSVs were compared by employing ANSYS´ HFSS, and a feasible fabrication process for coaxial-annular TSV was suggested. It could be concluded that: 1) a 1.6-μm (22.2%) drop of KOZ for coaxial-annular TSV could be reached as compared with that of coaxial TSV; 2) coaxialannular TSV was proved to offer the same superior signal integrity with coaxial TSV, improving S21 by about 93% at 5 GHz and 60% at 20 GHz compared with ordinary cylindrical and annular TSVs; and 3) the coaxial-annular TSV is realizable.
  • Keywords
    finite element analysis; integrated circuit modelling; thermal stresses; three-dimensional integrated circuits; ANSYS HFSS; KOZ; TSV material; TSV size; TSV-induced stress; analytical model; coaxial through-silicon-via; coaxial-annular TSV structure; copper plasticity effect; electrical characteristics; fabrication process; finite element method; frequency 20 GHz; frequency 5 GHz; inner metal plating ratio; keep-out-zone reduction; signal integrity; thermal stress; Analytical models; Finite element analysis; Metals; Silicon; Stress; Through-silicon vias; 3-D; integration; keep-out-zone (KOZ); thermal stress; through-silicon-via (TSV); through-silicon-via (TSV).;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/TED.2014.2330838
  • Filename
    6845357