Single-Event Performance and Layout Optimization of Flip-Flops in a 28-nm Bulk Technology

Author

Lilja, K. ; Bounasser, M. ; Wen, S.-J. ; Wong, Rita ; Holst, J. ; Gaspard, N. ; Jagannathan, Sarangapani ; Loveless, D. ; Bhuva, Bharat

Author_Institution

Robust Chip Inc., Pleasanton, CA, USA

Volume

60

Issue

4

fYear

2013

fDate

Aug. 2013

Firstpage

2782

Lastpage

2788

Abstract

Alpha, neutron, and heavy-ion single-event measurements were performed on both high-performance and hardened flip-flop designs in a 28-nm bulk CMOS technology. The experimental results agree very well with simulation predictions and confirm that event error rates can be reduced dramatically using effective layout design.

Keywords

CMOS logic circuits; circuit simulation; flip-flops; integrated circuit layout; logic design; optimisation; radiation hardening (electronics); alpha single-event measurement; bulk CMOS technology; event error rate; flip-flop design; heavy-ion single-event measurement; layout optimization design; neutron single-event measurement; simulation prediction; single-event performance; size 28 nm; Analytical models; Error analysis; Integrated circuit modeling; Layout; Neutrons; Predictive models; Solid modeling; Dual-interlocked cell (DICE); Layout design through Error Aware Positioning (LEAP); radhard design methodology; radiation hardening; radiation hardening by design; single-event effect; single-event upsets (SEU); soft error;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2013.2273437

Filename

6575154