Dynamic fault recovery using partial reconfiguration for highly reliable FPGAs

FPGAs are becoming more popular in the domain of safety-critical applications (such as space applications) due to their high performance, re-programmability and reduced development cost. Such systems require FPGAs with self-detection and self-repairing capabilities in order to cope with errors due to the harsh conditions that usually exist in such environments. In this paper, a new dynamic fault recovery technique is proposed using the runtime partial reconfiguration (PR) property in FPGAs. It focuses on open interconnect faults and relies on specifying a Partially Reconfigurable block in the FPGA that is only used during the recovery process after the failure of the first module in the system. The technique uses only one location to recover from errors in any of the FPGA´s modules. Accordingly, it requires less area overhead when compared to other techniques.