• DocumentCode
    732235
  • Title

    Variability budgetin pulsed flip-flops

  • Author

    Alioto, Massimo ; Palumbo, Gaetano ; Consoli, Elio

  • Author_Institution
    ECE - Nat. Univ. of Singapore (Singapore), Singapore, Singapore
  • fYear
    2015
  • fDate
    7-10 June 2015
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    In this paper, the impact of variations on the most representative pulsed flip-flops topologies is comparatively evaluated in 65-nm CMOS. The analysis explicitly considers fundamental sources of variations such as process, voltage, temperature and clock slope. For each FF topology, the variations are statistically evaluated through Monte Carlo simulations and they explicitly include the non-negligible impact of layout parasitics.
  • Keywords
    CMOS logic circuits; flip-flops; CMOS; Monte Carlo simulations; pulsed flip-flops; Clocks; Delays; Flip-flops; Sensitivity; Standards; Temperature sensors; Topology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    New Circuits and Systems Conference (NEWCAS), 2015 IEEE 13th International
  • Conference_Location
    Grenoble
  • Type

    conf

  • DOI
    10.1109/NEWCAS.2015.7182003
  • Filename
    7182003
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=732235