Design considerations for low-noise transconductance amplifiers in 28nm UTBB-FDSOI

Author

Danilovic, D. ; Cathelin, A. ; Vladimirescu, A. ; Nikolic, B.

Author_Institution

STMicroelectron., Crolles, France

fYear

2015

fDate

7-10 June 2015

Firstpage

1

Lastpage

4

Abstract

This paper presents a methodology for selecting the architecture and optimizing the circuit design for the first block in a current-mode receiver chain, the low noise transconductance amplifier (LNTA). This methodology includes system-level considerations to select circuit design techniques for noise cancellation, linearity improvement and power reduction. The methodology is applied on an LNTA design in 28nm UTBB-FDSOI CMOS. The selected amplifier topology is designed to operate at 2.4GHz with a transconductance of 15mS. It achieves 2.67dB noise figure (NF), 1dB compression point (P1dB) of -7dBm, 9.5dBm input third order intercept point (IIP3) and consumes 1.5mA from a 1.2V supply.

Keywords

current-mode circuits; integrated circuit design; low noise amplifiers; operational amplifiers; silicon-on-insulator; UTBB-FDSOI; amplifier topology; circuit design; current 1.5 mA; current-mode receiver chain; frequency 2.4 GHz; linearity improvement; low-noise transconductance amplifiers; noise cancellation; noise figure 2.67 dB; power reduction; size 28 nm; voltage 1.2 V; CMOS integrated circuits; CMOS technology; Noise cancellation; Noise measurement; Receivers; Transconductance; Low noise transconductance amplifier(LNTA); UTBB-FDSOI; current-mode receiver; noise cancellation;

fLanguage

English

Publisher

ieee

Conference_Titel

New Circuits and Systems Conference (NEWCAS), 2015 IEEE 13th International

Conference_Location

Grenoble

Type

conf

DOI

10.1109/NEWCAS.2015.7182012

Filename

7182012