Design approaches for mode decision in HEVC encoder exploiting parallelism at CTB level

As CPU technology trend is strongly moving towards multi-core architectures, HEVC tried to embrace the parallel processing trend to possible extent. Hence, HEVC exploits some of the parallel processing capabilities like tiles, slices and WPP at frame level (Sullivan et al., 2012). Although slices, tiles and WPP can be used to achieve parallelism, they might end-up degrading either visual quality or compression efficiency. To address this problem, this paper tries to summarize/exploit the possible parallel processing capabilities of HEVC at Coding Tree Block (CTB) level with insignificant compromise in video quality and compression.