Binding and scheduling for system-level synthesis of ARM-core with multiple DSPs

In order to meet the requirements of multimedia, network, etc, the modern embedded system is combined RISC core with DSP cores in one processor. Such a heterogeneous multi-core processor architecture has enormous potential for optimization, but requires a system-level design and synthesis. Our approach is to take a specification of the behavior required of a system and a set of constraints and goals to be satisfied, and to find a structure that implements the behavior while meeting the goals and constraints. We consider the system synthesis problem as three sub-problem: selection of appropriate processing cores, binding and scheduling of the instructions of the given task to the selected processing cores, and the performance evaluation. We present an integrated approach to mapping the given task to a heterogeneous multi-core processor architecture at run-time, which can automate selection, binding and scheduling. We also present a methodology to optimize the system for the given task. The optimization objective is to minimize the time consumption of the SOC, while still providing the required Quality of Service. We have implemented our algorithms on a Vox, and applied it to a MPEG-4 decoder. Our experimental results have shown that our algorithm is adapted to solve this problem and is applied to explore the design space of video-codec implementaion. Experimental studies show this approach is flexible, scalable and performance looks promising.