Estimation of remaining life using embedded SRAM for wearout parameter extraction

Author

Woongrae Kim ; Chang-Chih Chen ; Taizhi Liu ; Soonyoung Cha ; Milor, Linda

Author_Institution

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

fYear

2015

fDate

18-19 June 2015

Firstpage

243

Lastpage

248

Abstract

Safety critical systems need methods for chips to monitor their health in the field. This paper proposes to use the embedded SRAM as a monitor of system health. The bit failures are tracked and the cause of each bit failure is diagnosed with on-chip built-in self test (BIST). The wearout model parameters are estimated from the diagnosis results and combined with system wearout simulation data to estimate the remaining lifetime of a system.

Keywords

SRAM chips; built-in self test; integrated circuit testing; life testing; semiconductor device reliability; wear testing; BIST; embedded SRAM; on-chip built-in self test; remaining life estimation; system health monitor; wearout parameter extraction; Circuit faults; Electric breakdown; Electromigration; Logic gates; SRAM cells; Stress; Backend dielectric breakdown; Bias temperature instability; Built-In Self-Test (BIST); Electromigration; Gate oxide breakdown; Lifetime; Stress-induced voiding; Wearout parameter;

fLanguage

English

Publisher

ieee

Conference_Titel

Advances in Sensors and Interfaces (IWASI), 2015 6th IEEE International Workshop on

Conference_Location

Gallipoli

Type

conf

DOI

10.1109/IWASI.2015.7184952

Filename

7184952