Single and multi-phase offset numerical estimation for CMOS hall effect devices

The present work is focused on characterizing the behaviour of Hall Effect devices integrated in a regular bulk 0.35 μm CMOS technology, by providing amongst other, numerical data regarding their sensitivity, single and multi-phase offset. Also, the paper investigates the parabolic variation of the residual offset with the biasing current and the encapsulation offset. Temperature drifts of the main parameters are also included. Three-dimensional physical models for the CMOS Hall structures have been developed, in order to analyze their performance.