Title :
Fault modeling and testing of through silicon via interconnections
Author :
Gerakis, Vasileios ; Katselas, Leonidas ; Hatzopoulos, Alkis
Author_Institution :
Dept. of Electr. & Comput. Eng., Aristotle Univ. of Thessaloniki, Thessaloniki, Greece
Abstract :
The case of a defected TSV that has been cracked at the point where an impurity or a void hole originally had been is analyzed in this study. A lumped analytical electrical circuit that models the behavior of this defect is proposed. TSV fault modeling offers assistance in developing new test methods that would improve the reliability of the 3D ICs. The structure is simulated using a commercial 3D resistance, capacitance and inductance extraction tool. A test method that determines the possible characteristics of the defect is presented.
Keywords :
integrated circuit interconnections; integrated circuit modelling; integrated circuit reliability; integrated circuit testing; three-dimensional integrated circuits; 3D IC; TSV; fault modeling; fault testing; lumped analytical electrical circuit; through silicon via interconnections; Decision support systems; Testing; 3D ICs; TSV; crack; fault modeling;
Conference_Titel :
On-Line Testing Symposium (IOLTS), 2015 IEEE 21st International
Conference_Location :
Halkidiki
DOI :
10.1109/IOLTS.2015.7229824
