Title :
Soft error immune latch under SEU related double-node charge collection
Author :
Katsarou, Katerina ; Tsiatouhas, Yiorgos
Author_Institution :
Dept. of Comput. Sci. & Eng., Univ. of Ioannina, Ioannina, Greece
Abstract :
The susceptibility of memory elements (latches, flip-flops) to soft errors is increased as CMOS technology scales down, due to multi-node charge collection by the impact of energetic particles on silicon. Existing design solutions provide partial or no immunity to SEUs that affect a pair of nodes. In this work, we propose a new latch topology, which provides complete protection from SEU related double node charge sharing. Simulations results and comparisons on a variety of SEU tolerant techniques are presented to evaluate the efficiency of the proposed latch.
Keywords :
CMOS logic circuits; flip-flops; network topology; radiation hardening (electronics); CMOS technology; SEU tolerant techniques; double node charge sharing; double-node charge collection; latch topology; memory elements susceptibility; multinode charge collection; soft error immune latch; CMOS integrated circuits; Latches; MOSFET; Silicon; Single event upsets; Topology; Transient analysis; SEU tolerant latch design; double node charge sharing SEUs; soft error tolerance;
Conference_Titel :
On-Line Testing Symposium (IOLTS), 2015 IEEE 21st International
Conference_Location :
Halkidiki
DOI :
10.1109/IOLTS.2015.7229830
