DocumentCode
735258
Title
A 4×9 Gb/s 1 pJ/b NRZ/multi-tone serial-data transceiver with crosstalk reduction architecture for multi-drop memory interfaces in 40nm CMOS
Author
Gharibdoust, Kiarash ; Tajalli, Armin ; Leblebici, Yusuf
Author_Institution
EPFL, Lausanne, Switzerland
fYear
2015
fDate
17-19 June 2015
Abstract
An aggregated 36 Gb/s low power 4-lanes mixed NRZ/multi-tone transceiver for multi-drop bus (MDB) memory interfaces is designed and fabricated in 40nm CMOS technology. The proposed architecture achieves 1 pJ/bit power efficiency in the entire link (TX + RX) for an MDB channel with 45 dB loss at 3 GHz. The multi-tone nature of the proposed transceiver is employed to properly reduce crosstalk (Xtalk) induced noise and to improve overall power efficiency.
Keywords
CMOS memory circuits; crosstalk; logic design; low-power electronics; transceivers; CMOS technology; MDB channel; MDB memory interfaces; NRZ-multitone serial-data transceiver; Xtalk; bit rate 36 Gbit/s; crosstalk reduction architecture; frequency 3 GHz; loss 45 dB; low power mixed NRZ-multitone transceiver; multidrop bus; multidrop memory interfaces; power efficiency; size 40 nm; CMOS integrated circuits; Clocks; Computer architecture; Crosstalk; Noise; Optical signal processing; Transceivers;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits (VLSI Circuits), 2015 Symposium on
Conference_Location
Kyoto
Print_ISBN
978-4-86348-502-0
Type
conf
DOI
10.1109/VLSIC.2015.7231253
Filename
7231253
Link To Document