A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface

Author

Chang-Kyo Lee ; Minsu Ahn ; Daesik Moon ; Kiho Kim ; Yoon-Joo Eom ; Won-Young Lee ; Jongmin Kim ; Sanghyuk Yoon ; Baekkyu Choi ; Seokhong Kwon ; Joon-Young Park ; Seung-Jun Bae ; Yong-Cheol Bae ; Jung-Hwan Choi ; Seong-Jin Jang ; Gyoyoung Jin

Author_Institution

DRAM Design Team, Samsung Electron., Hwasung, South Korea

fYear

2015

fDate

17-19 June 2015

Abstract

A 6.4Gb/s TX-interleaving (TI) technique at sub-1V supply voltage is implemented with 25nm DRAM process for the future mobile DRAM interface which requires 51.2 GBps (2X Bandwidth of LPDDR4). A newly proposed 2-channel TX interleaving technique with a bootstrapping switch can save power consumption drastically by eliminating repeaters, while operating at 6.4 Gb/s with 40 % enhancement of I/O power efficiency compared to that of the LPDDR4.

Keywords

DRAM chips; bootstrap circuits; low-power electronics; transmitters; 2-channel TX interleaving technique; DRAM process; I-O power efficiency; LPDDR4; TX-interleaving technique; bit rate 6.4 Gbit/s; bootstrapping switch; future mobile DRAM interface; power consumption; size 25 nm; Clocks; Power demand; Random access memory; Repeaters; Switches; Transceivers; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSI Circuits), 2015 Symposium on

Conference_Location

Kyoto

Print_ISBN

978-4-86348-502-0

Type

conf

DOI

10.1109/VLSIC.2015.7231254

Filename

7231254