Title :
A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme, and duty-training circuit for mobile applications
Author :
Hae-Kang Jung ; Jaemo Yang ; Jeonghun Lee ; Hyeongjun Ko ; Hyuk Lee ; Taeksang Song ; Jongjoo Shim ; Sang-Kwon Lee ; Keunsoo Song ; Dong-Kyun Kim ; Hyungsoo Kim ; Yunsaing Kim
Author_Institution :
High-Speed Interface Design Team, SK hynix, Icheon, South Korea
Abstract :
A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme and Duty-Training Circuit (DTC) is presented. A Low Voltage-Swing Terminated Logic (LVSTL) driver using 4-to-1 multiplexer is implemented to the transmitter. A DTC to adjust the CK duty is implemented to the receiver. In addition, a ZQ calibration scheme for Multi-VOH level is also presented. Designed schemes are compatible with the LPDDR4 standard. Power efficiency for the I/O interface is about 2.3mW/Gb/s/pin with 1.1V supply in 2y-nm DRAM process, which is 31% lower than that of LPDDR3.
Keywords :
DRAM chips; driver circuits; low-power electronics; multiplexing equipment; radio receivers; radio transmitters; 2y-nm DRAM process; 4-to-1 multiplexer; LPDDR4 I/O interface; LVSTL driver; ZQ calibration scheme; duty-training circuit; equalization scheme; low voltage-swing terminated logic driver; mobile applications; multiVOH level; radio receiver; radio transmitter; voltage 1.1 V; Calibration; Computer architecture; Random access memory; Receivers; Standards; Transistors; Transmitters; DCC; DRAM Interface; LVSTL; N-over-N driver; pre-emphasis; slew-rate control;
Conference_Titel :
VLSI Circuits (VLSI Circuits), 2015 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-86348-502-0
DOI :
10.1109/VLSIC.2015.7231255
