Title :
A 100-GbE reverse gearbox IC in 40nm CMOS for supporting legacy 10- and 40-GbE standards
Author :
Taehun Yoon ; Joon-Yeong Lee ; Kwangseok Han ; Jeongsup Lee ; Sangeun Lee ; Taeho Kim ; Hyosup Won ; Jinho Park ; Hyeon-Min Bae
Author_Institution :
KAIST, Daejeon, South Korea
Abstract :
This paper presents the industry´s first low-power 100-Gigabit Ethernet (GbE) multi-link gearbox (MLG) IC, which facilitates transport of independent 10-GbE and 40-GbE signals to 4×25G physical layers implementing 100GBASE-R. The IC consumes only 1.37-W while implementing complicated reverse gearbox functionality. The measured TX jitter from the 25-Gb/s lane is 1.6-psrms, and the recovered clock jitter is 0.5-psrms. The measured RX input sensitivity for a BER 10-12 is 42-mVppd. The proposed gearbox IC, fabricated in a 40nm CMOS process, occupies 3.7×3.4-mm2. The power consumption of RX and TX in 25G interfaces are 47-mW and 51-mW, respectively, and those of a 10G interfaces are 24-mW and 25-mW, respectively. Gearbox functionalities are verified with embedded self-test logics.
Keywords :
CMOS integrated circuits; error statistics; local area networks; low-power electronics; timing jitter; 10-GbE standards; 100GBASE-R; 40-GbE standards; BER; CMOS process; bit rate 25 Gbit/s; complicated reverse gearbox functionality; low-power 100-Gigabit Ethernet; measured TX jitter; multilink gearbox IC; physical layers; power 1.37 mW; power 24 mW; power 25 mW; power 47 mW; power 51 mW; power consumption; recovered clock jitter; reverse gearbox IC; size 40 nm; CMOS integrated circuits; CMOS technology; Clocks; Jitter; Phase locked loops; Synchronization; 100-GbE; CDR; MLG 2.0; Reverse gearbox IC; transceiver;
Conference_Titel :
VLSI Circuits (VLSI Circuits), 2015 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-86348-502-0
DOI :
10.1109/VLSIC.2015.7231262
