DocumentCode
735268
Title
A 40-Gb/s 9.2-mW CMOS equalizer
Author
Manian, Abishek ; Razavi, Behzad
Author_Institution
Univ. of California, Los Angeles, Los Angeles, CA, USA
fYear
2015
fDate
17-19 June 2015
Abstract
A 40-Gb/s equalizer incorporates a one-stage CTLE with 5.5-dB boost, a one-tap discrete-time linear equalizer with 5.4-dB boost, a two-tap halfrate/quarter-rate DFE, and charge-steering techniques. Realized in 45-nm CMOS technology, the equalizer achieves BER <; 10-12 with a clock phase margin of 0.28 UI with a channel loss of 20 dB at Nyquist.
Keywords
CMOS integrated circuits; decision feedback equalisers; CMOS equalizer; channel loss; charge-steering techniques; clock phase margin; one-tap discrete-time linear equalizer; two-tap halfrate/quarter-rate DFE; Decision feedback equalizers; Gain; Generators; Latches; Loss measurement; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits (VLSI Circuits), 2015 Symposium on
Conference_Location
Kyoto
Print_ISBN
978-4-86348-502-0
Type
conf
DOI
10.1109/VLSIC.2015.7231266
Filename
7231266
Link To Document