DocumentCode
735273
Title
4.2 pW timer for heavily duty-cycled systems
Author
Nadeau, Phillip M. ; Paidimarri, Arun ; Chandrakasan, Anantha P.
Author_Institution
Massachusetts Inst. of Technol., Cambridge, MA, USA
fYear
2015
fDate
17-19 June 2015
Abstract
An ultra-low energy wake-up timer suitable for heavily duty-cycled systems is presented. A prototype implemented in 0.18μm CMOS consumes 4.2pW of power for 18Hz of oscillation (0.23pJ/cycle). A dynamic 3-stage architecture, duty-cycled current-source, and low operating voltage (0.6V) enabled by a voltage boost circuit all contribute to the improved efficiency.
Keywords
CMOS integrated circuits; constant current sources; low-power electronics; oscillations; CMOS integrated circuit; duty-cycled current-source; dynamic 3-stage architecture; frequency 18 Hz; heavily duty-cycled systems; oscillation; power 4.2 pW; size 0.18 mum; ultra-low energy wake-up timer; voltage 0.6 V; voltage boost circuit; Gate leakage; Latches; Oscillators; Short-circuit currents; Temperature measurement; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits (VLSI Circuits), 2015 Symposium on
Conference_Location
Kyoto
Print_ISBN
978-4-86348-502-0
Type
conf
DOI
10.1109/VLSIC.2015.7231272
Filename
7231272
Link To Document