• DocumentCode
    735287
  • Title

    7.4μW Ultra-high slew-rate pseudo single-stage amplifier driving 0.1-to-15nF capacitive load with >69° phase margin

  • Author

    Sung-Wan Hong ; Gyu-Hyeong Cho

  • Author_Institution
    DMC R&D Center, Samsung Electron., Suwon, South Korea
  • fYear
    2015
  • fDate
    17-19 June 2015
  • Abstract
    To achieve ultra-high slew-rate with stable operation under wide capacitive load range, pseudo single-stage amplifier is proposed in this paper. The proposed amplifier achieves widest capacitive load drivability (x150). Also, this work achieves at least 151 times larger FOM for slew-rate compared to state-of-the-art works. This chip was fabricated using a 0.18 μm CMOS process with area of 0.0021 mm2.
  • Keywords
    CMOS integrated circuits; amplifiers; CMOS process; capacitive load; size 0.18 mum; ultra-high slew-rate pseudo single-stage amplifier; CMOS process; Capacitors; Feedback loop; Logic gates; Mirrors; Resistance; Transient analysis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits (VLSI Circuits), 2015 Symposium on
  • Conference_Location
    Kyoto
  • Print_ISBN
    978-4-86348-502-0
  • Type

    conf

  • DOI
    10.1109/VLSIC.2015.7231297
  • Filename
    7231297