A 23mW face recognition accelerator in 40nm CMOS with mostly-read 5T memory

Author

Dongsuk Jeon ; Qing Dong ; Yejoong Kim ; Xiaolong Wang ; Shuai Chen ; Hao Yu ; Blaauw, David ; Sylvester, Dennis

Author_Institution

Univ. of Michigan, Ann Arbor, MI, USA

fYear

2015

fDate

17-19 June 2015

Abstract

This paper presents a face recognition accelerator for HD (1280×720) images. The proposed design detects faces from the input image using cascaded classifiers. A SVM (Support Vector Machine) performs face recognition based on features extracted by PCA (Principal Component Analysis). Algorithm optimizations including a hybrid search scheme that reduces the workload for face detection by 12×. A new mostly-read 5T memory reduces bitcell area by 7.2% compared to a conventional 6T bitcell while achieving significantly better read reliability and voltage scalability due to a decoupled read path. The resulting design consumes 23mW while processing both face detection and recognition in real time at 5.5 frames/s throughput.

Keywords

CMOS memory circuits; face recognition; feature extraction; image classification; optimisation; principal component analysis; search problems; support vector machines; CMOS; HD images; PCA; SVM; bitcell area; cascaded classifiers; decoupled read path; face detection; face recognition accelerator; feature extraction; hybrid search scheme; mostly-read 5T memory; power 23 mW; principal component analysis; read reliability; size 40 nm; support vector machine; voltage scalability; Face; Face detection; Face recognition; Feature extraction; Principal component analysis; Random access memory; Support vector machines;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSI Circuits), 2015 Symposium on

Conference_Location

Kyoto

Print_ISBN

978-4-86348-502-0

Type

conf

DOI

10.1109/VLSIC.2015.7231322

Filename

7231322