A 794Mbps 135mW iterative detection and decoding receiver for 4×4 LDPC-coded MIMO systems in 40nm

Author

Wei-Hsuan Wu ; Wei-Cheng Sun ; Chia-Hsiang Yang ; Yeong-Luh Ueng

Author_Institution

Nat. Tsing Hua Univ., Hsinchu, Taiwan

fYear

2015

fDate

17-19 June 2015

Abstract

A low-density parity-check (LDPC)-coded multiple-input multiple-output (MIMO) systems with iterative detection and decoding (IDD) chip is integrated in 1.33mm² in 40nm CMOS. The maximum gross throughput is 794Mb/s for a 4×4 16-QAM configuration at 288MHz. The chip dissipates 135mW at 0.9V, achieving an energy efficiency of 170pJ/bit. Compared to non-IDD receivers, composed of state-of-the art MIMO detectors and LDPC decoders, this work achieves even higher area and energy efficiencies, despite the improved error performance.

Keywords

CMOS integrated circuits; MIMO communication; iterative decoding; parity check codes; quadrature amplitude modulation; radio receivers; signal detection; 16-QAM configuration; CMOS integrated circuit; LDPC; MIMO systems; bit rate 794 Mbit/s; iterative decoding receiver; iterative detection receiver; low density parity check code; multiple input multiple output systems; power 135 mW; voltage 0.9 V; Decoding; Detectors; MIMO; Memory management; Nickel; Parity check codes; Receivers;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSI Circuits), 2015 Symposium on

Conference_Location

Kyoto

Print_ISBN

978-4-86348-502-0

Type

conf

DOI

10.1109/VLSIC.2015.7231340

Filename

7231340