A 16-channel wireless neural interfacing SoC with RF-powered energy-replenishing adiabatic stimulation

Author

Ha, S. ; Akinin, A. ; Park, J. ; Kim, C. ; Wang, H. ; Maier, C. ; Cauwenberghs, G. ; Mercier, P.P.

Author_Institution

Univ. of California, San Diego, La Jolla, CA, USA

fYear

2015

fDate

17-19 June 2015

Abstract

This paper presents a fully-integrated 16-channel wireless neural interfacing SoC that employs an adiabatic stimulator powered directly from a 190-MHz on-chip antenna to eliminate bulky external components while simultaneously avoiding rectifier and regulator losses. Using a charge replenishing architecture, the stimulator outputs up to 145-μA, while achieving a 63.1% charge replenishing ratio and a stimulation efficiency factor of 6.0. Analog front-ends (AFEs) and telemetry circuitry are also included.

Keywords

brain-computer interfaces; integrated circuit interconnections; radiofrequency integrated circuits; rectifiers; system-on-chip; wireless channels; AFE; RF-powered energy-replenishing adiabatic stimulation; analog front-end; channel wireless neural interfacing SoC; frequency 190 MHz; on-chip antenna; rectifier; regulator losses; telemetry circuitry; Current measurement; Electrodes; Generators; Rectifiers; System-on-chip; Voltage measurement; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSI Circuits), 2015 Symposium on

Conference_Location

Kyoto

Print_ISBN

978-4-86348-502-0

Type

conf

DOI

10.1109/VLSIC.2015.7231341

Filename

7231341