Title :
56Gb/s PAM4 and NRZ SerDes transceivers in 40nm CMOS
Author :
Jri Lee ; Ping-Chuan Chiang ; Chih-Chi Weng
Author_Institution :
Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
This paper presents 56Gb/s PAM4 and NRZ SerDes transceivers (TRXs), designed and fabricated in advance CMOS technology. Incorporating broadband techniques, noise suppression skills, and clock extraction circuits, this work demonstrates feasibility of 56Gb/s SerDes and compares tradeoffs between the two data format.
Keywords :
CMOS integrated circuits; mixed analogue-digital integrated circuits; modulators; pulse amplitude modulation; CMOS integrated circuit; NRZ; PAM4; SerDes transceiver; bit rate 56 Gbit/s; broadband technique; clock extraction circuits; noise suppression; serializer-deserializer transceiver; size 40 nm; Bandwidth; Clocks; Decoding; Equalizers; Jitter; Optical signal processing; Sensitivity;
Conference_Titel :
VLSI Circuits (VLSI Circuits), 2015 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-86348-502-0
DOI :
10.1109/VLSIC.2015.7231346
