• DocumentCode
    735320
  • Title

    56Gb/s PAM4 and NRZ SerDes transceivers in 40nm CMOS

  • Author

    Jri Lee ; Ping-Chuan Chiang ; Chih-Chi Weng

  • Author_Institution
    Nat. Taiwan Univ., Taipei, Taiwan
  • fYear
    2015
  • fDate
    17-19 June 2015
  • Abstract
    This paper presents 56Gb/s PAM4 and NRZ SerDes transceivers (TRXs), designed and fabricated in advance CMOS technology. Incorporating broadband techniques, noise suppression skills, and clock extraction circuits, this work demonstrates feasibility of 56Gb/s SerDes and compares tradeoffs between the two data format.
  • Keywords
    CMOS integrated circuits; mixed analogue-digital integrated circuits; modulators; pulse amplitude modulation; CMOS integrated circuit; NRZ; PAM4; SerDes transceiver; bit rate 56 Gbit/s; broadband technique; clock extraction circuits; noise suppression; serializer-deserializer transceiver; size 40 nm; Bandwidth; Clocks; Decoding; Equalizers; Jitter; Optical signal processing; Sensitivity;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits (VLSI Circuits), 2015 Symposium on
  • Conference_Location
    Kyoto
  • Print_ISBN
    978-4-86348-502-0
  • Type

    conf

  • DOI
    10.1109/VLSIC.2015.7231346
  • Filename
    7231346
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=735320