A 25-Gb/s, −10.8-dBm input sensitivity, PD-bandwidth tolerant CMOS optical receiver

This paper describes a 25-Gb/s energy-efficient CMOS optical receiver with high input sensitivity. By incorporating a current boosting preamplifier with time-interleaved integrating-type optical receiver, it also circumvents CID issue with high PD bandwidth tolerance. Experimental results show that the receiver can achieve 25-Gb/s operation by integrating with a 9-GHz or 17-GHz GaAs PD. Input sensitivities in the two cases are -7.2 dBm (w/i 9-GHz PD) and -10.8 dBm (w/i 17-GHz PD) respectively for BER of less than 10^-12. The energy efficiency is 1.13 pJ/bit. Fabricated in TSMC 40-nm CMOS technology, the core circuit occupies a chip area of 0.007 mm² only.