Title :
Design and demonstration of reliability-aware Ge gate stacks with 0.5 nm EOT
Author :
Lu, C. ; Lee, C.H. ; Nishimura, T. ; Toriumi, A.
Author_Institution :
Department of Materials Engineering, The University of Tokyo
Abstract :
This paper reports a novel material/process-based design for reliability-aware Ge gate stack for the first time. Initially good characteristics of Ge gate stacks do not necessarily guarantee the long-term device reliability. To overcome the big hurdle, we have investigated the stability of GeO2 network as well as the formation of new high-k. The very robust Ge gate stack with both 0.5 nm EOT and sufficiently low Dit is demonstrated.
Keywords :
Hafnium compounds; High K dielectric materials; Logic gates; Resistance; Robustness; Stress;
Conference_Titel :
VLSI Circuits (VLSI Circuits), 2015 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
978-4-86348-502-0
DOI :
10.1109/VLSIC.2015.7231383
