Design and demonstration of reliability-aware Ge gate stacks with 0.5 nm EOT

This paper reports a novel material/process-based design for reliability-aware Ge gate stack for the first time. Initially good characteristics of Ge gate stacks do not necessarily guarantee the long-term device reliability. To overcome the big hurdle, we have investigated the stability of GeO2 network as well as the formation of new high-k. The very robust Ge gate stack with both 0.5 nm EOT and sufficiently low Dit is demonstrated.