A computational geometry based cell migration technique for VLSI placement problem

The movement of preplaced cells among a prescribed existing placement to solve a set of worst designed placement related facts - for example, routing problems, timings, integrity of signals and distribution of heat. To solve this design related problems one has to prefer to translate the design. The translation should be as small as possible while retaining the originality of the placement integrity. The current paper proposes a new algorithmic treatment of the above problem through computational geometry. Our theoretical proposals established through experimental proofs.