A 405MHz integer-N CMOS PLL for implantable biomedical application

This work is dedicated to a Phase Locked Loop design that works with a sub 1GHz frequency band. Medical Implant Communication Service operates at 402-405 MHz frequency of operation. The PLL design used in this paper uses a novel two stage ring VCO that can generate 179MHz to 438MHz by changing the control voltage from 0.3-V to 1-V. The worst case phase noise of -106dBc/Hz is obtained at an offset of 1MHz. The VCO is controlled by changing the resistance in the forward path by varying the gate voltage of the transmission gate. Thus the design challenge to achieve oscillation at two stages is achieved. For small frequency to have small size device is not possible in conventional design has been achieved in this design. The lock in time of the PLL is 8μS with a charge pump current of 100μA. The PLL architecture consumes 280μW of power from a supply voltage of 1-V. The loop filter and its stability analysis have been verified by MATLAB. The Simulink model has been developed in order to verify the theoretical operation of the PLL. The Transistor level analysis has been done using Cadence virtuoso 90nm CMOS technology.