A 0.8 dB NF, 4.6 dBm IIP3, 1.8–2.2 GHz, low-power LNA in 130 nm RF SOI CMOS technology

Author

Noori, Hossein ; Sanner, Miles ; Yanduru, Naveen

Author_Institution

Peregrine Semicond. Corp., San Diego, CA, USA

fYear

2015

fDate

23-24 April 2015

Firstpage

1

Lastpage

4

Abstract

A 1.8-2.2 GHz CMOS LNA featuring a record 0.8dB noise figure is reported using an inductively-degenerated cascode topology combined with floating-body transistors and high-Q passives on an SOI substrate. The LNA achieves 11 dB of power gain while consuming 6.6 mW dc power from a 1.5V supply. The LNA covers Bands 1, 2, and 3 of 3GPP, and is suitable for LTE terminal applications. IIP3 of +4.6dBm and Input P1dB compression point of -3.5 dBm are measured. The LNA occupies an area of 0.8mm².

Keywords

CMOS integrated circuits; low noise amplifiers; low-power electronics; radiofrequency integrated circuits; CMOS LNA; LTE terminal applications; RF SOI CMOS technology; SOI substrate; floating-body transistors; frequency 1.8 GHz to 2.2 GHz; gain 11 dB; high-Q passives; inductively-degenerated cascode topology; low noise amplifiers; low-power LNA; noise figure 0.8 dB; power 6.6 mW; size 130 nm; voltage 1.5 V; CMOS integrated circuits; Electrostatic discharges; Impedance matching; Inductors; Noise figure; Radio frequency; Low-Noise Amplifier (LNA); linearity; low-power; mobile communication; silicon-on-insulator (SOI);

fLanguage

English

Publisher

ieee

Conference_Titel

Wireless and Microwave Circuits and Systems (WMCS), 2015 Texas Symposium on

Conference_Location

Waco, TX

Type

conf

DOI

10.1109/WMCaS.2015.7233203

Filename

7233203