Designing of Phase and Frequency Detector for low Jitter and high speed applications

A novel architecture of Phase and Frequency Detector is introducing in this paper. This Tri-state transmission gate PFD (Tt-PFD) is designed with transmission gates by using only 12 transistors and conveying functional characteristics of traditional PFD with an improved performance. Proposed PFD is used to generate a qualitative clock signal at high frequency and low Jitter Phase Locked Loop (PLL) applications. Phase noise of this PFD is −164.7dBc/Hz at 1MHz offset and its maximum operating frequency 5.5GHz with 12ps jitter. It consumes 6.9µw when operates at 50MHz clock frequency with 1.8v voltage supply. This Tt-PFD implemented in cadence 0.18µm TSMC CMOS process.