Optimize the PTM Circuit Calculation Using DEO Algorithm

At present, the integrated circuit is gradually deep sub-micron to nano-scale electronic devices based on silicon technology, will soon get to the normal work of the theory of "limit". On the other hand, in order to reduce the power consumption, the working voltage of integrated circuits has been reduced, at the same time, with the working frequency of the devices of continuous improvement, effect of nano-scale integrated circuit will be very vulnerable to the device itself perturbation and external disturbances, the transient fault and circuit operation. Reliability design of nanometer scale integrated circuits (soft error tolerance design) can be effective in suppressing circuit soft error, be regarded as a development direction of next generation of integrated circuit design. Probabilistic transfer matrix (PTM) can effectively estimate the integrated circuit soft error, resulting in chip production before estimating the fault tolerance of the chip. But PTM has large amount of calculation, extreme memory consumption problems in the process of calculation, the influence of practicality. This paper presents an improved algorithm based on Dynamic Ordering Evaluation (DEO) for PTM. Simulation results show that, this algorithm can effectively reduce the PTM computation, improve the computational speed.