Design and Performance Analysis of a 866-MHz Low-Power Optimized CMOS LNA for UHF RFID

An optimized 866 MHz CMOS LNA for UHF radio-frequency identification reader is presented. It achieves simultaneous impedance and minimum F_min noise matching at a very low-power drain of 850 μW from a 0.7-V supply voltage. Compared to other GHz LNA designs, this UHF LNA design using sub-1 V supply voltage is quite challenging due to the inductor size and bias drain-related noise factor degradation. The LNA was fabricated using the 130-nm IBM CMOS process. Compared to previously reported narrow-band LNA designs, inclusion of the finite g_ds effect is found to improve the nanometric design optimization. The low-cost packaged LNA was tested using external lumped element and microstrip line matching. The LNA delivered a power gain (S₂₁) of ≈17 dB and an input power reflection (S11 @ 866 MHz) of ≈ -30 dB. It had a minimum pass-band noise figure of around 2.2 dB and a third-order input-referred intercept point of ≈ -11.5 dBm.