• DocumentCode
    737830
  • Title

    Computing Two-Pattern Test Cubes for Transition Path Delay Faults

  • Author

    Pomeranz, Irith

  • Author_Institution
    Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
  • Volume
    21
  • Issue
    3
  • fYear
    2013
  • fDate
    3/1/2013 12:00:00 AM
  • Firstpage
    475
  • Lastpage
    485
  • Abstract
    Considering full-scan circuits, incompletely-specified tests, or test cubes, are used for test data compression. When considering path delay faults, certain specified input values in a test cube are needed only for determining the lengths of the paths associated with detected faults. Path delay faults, and therefore, small delay defects, would still be detected if such values are unspecified. The goal of this paper is to explore the possibility of increasing the number of unspecified input values in a test set for path delay faults by unspecifying such values in order to make the test set more amenable to test data compression. Experimental results indicate that significant numbers of such values exist. The proposed procedure unspecifies them gradually to obtain a series of test sets with increasing numbers of unspecified values and decreasing path lengths. Experimental results also indicate that filling the unspecified values randomly (as with some test data compression methods) recovers some or all of the path lengths associated with detected path delay faults. The procedure uses a matching of the sets of detected faults for the comparison of path lengths.
  • Keywords
    circuit reliability; circuit testing; data compression; delays; fault diagnosis; full-scan circuits; path lengths; small delay defects; test data compression methods; transition path delay faults; two-pattern test cubes; Circuit faults; Clocks; Compaction; Delay; Fault detection; Test data compression; Very large scale integration; Full-scan circuits; path delay faults; test cubes; transition faults; two-pattern tests;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2012.2188727
  • Filename
    6172636