Spur-Reduction Frequency Synthesizer Exploiting Randomly Selected PFD

Author

Te-Wen Liao ; Jun-Ren Su ; Chung-Chih Hung

Author_Institution

Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

21

Issue

3

fYear

2013

fDate

3/1/2013 12:00:00 AM

Firstpage

589

Lastpage

592

Abstract

This brief presents a low-spur phase-locked loop (PLL) system for wireless applications. The low-spur frequency synthesizer randomizes the periodic ripples on the control voltage of the voltage-controlled oscillator to reduce the reference spur at the output of the PLL. A novel random clock generator is presented to perform the random selection of the phase frequency detector control for the charge pump in locked state. The proposed frequency synthesizer was fabricated in a TSMC 0.18-μm CMOS process. The proposed PLL achieved phase noise of -93 dBc/Hz with a 600-kHz offset frequency and reference spurs below -72 dBc.

Keywords

CMOS analogue integrated circuits; clocks; frequency control; frequency synthesizers; phase control; phase locked oscillators; voltage control; voltage-controlled oscillators; PLL; TSMC CMOS process; charge pump; locked state; low-spur phase-locked loop system; periodic ripples; phase frequency detector control; random selected PFD; size 0.18 mum; spur-reduction frequency synthesizer; voltage-controlled oscillator; wireless applications; Charge pumps; Clocks; Frequency synthesizers; Generators; Phase locked loops; Phase noise; Voltage-controlled oscillators; Low spur synthesizer; phase-locked loop (PLL); voltage-controlled oscillator (VCO);

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2012.2190118

Filename

6176004