DocumentCode :
738238
Title :
A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme
Author :
Ohsawa, Takashi ; Koike, Hideaki ; Miura, Shun ; Honjo, Hiroaki ; Kinoshita, Keizo ; Ikeda, Shoji ; Hanyu, Takahiro ; Ohno, Hideo ; Endoh, Tetsuo
Author_Institution :
Center for Spintronics Integrated Syst., Tohoku Univ., Sendai, Japan
Volume :
48
Issue :
6
fYear :
2013
fDate :
6/1/2013 12:00:00 AM
Firstpage :
1511
Lastpage :
1520
Abstract :
A 1 Mb nonvolatile embedded memory using a four transistor and two spin-transfer-torque (STT) magnetic tunnel junction (MTJ) cell is designed and fabricated to demonstrate its zero standby power and high performance. The power supply voltages of 32 cells along a word line (WL) are controlled simultaneously by a power line (PL) driver to eliminate the standby power without impact on the access time. This fine-grained power gating scheme also optimizes the trade-off between macro size and operation power. The butterfly curve for the cell is measured to be asymmetric as predicted, enhancing the cell´s static noise margin (SNM) for data retention. The scaling of 1 Mb macro size is compared with that of the 6T SRAM counterpart, indicating that the former will become smaller than the latter at 45 nm technology node and beyond by moderately thinning its tunnel dielectrics (MgO) in accordance with the shrink of the MTJ´s cross sectional area. The operation current of the macro is also shown to be almost unchanged over generations, while that of the 6T SRAM increases exponentially due to the degradation of MOSFET off-current as the device scales.
Keywords :
MOSFET; SRAM chips; embedded systems; magnetic tunnelling; 4T2MTJ cell; 6T SRAM; MOSFET off-current; MTJ cross sectional area; PL driver; SNM; STT-MTJ cell; WL; butterfly curve; cell static noise margin; fine-grained power gating scheme; nonvolatile embedded memory; power line driver; size 45 nm; spin-transfer-torque magnetic tunnel junction cell; storage capacity 1 Mbit; transistor; tunnel dielectrics; word length 32 bit; word line; Computer architecture; MOSFET; Magnetic tunneling; Microprocessors; Nonvolatile memory; Random access memory; Switches; Break-even time (BET); embedded memory; magnetic tunnel junction (MTJ); nonvolatile memory; power gating; power-off time; spin-transfer torque random access memory (STT-RAM); static noise margin (SNM); static random access memory (SRAM); wake-up time;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2013.2253412
Filename :
6495490
Link To Document :
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