• DocumentCode
    739029
  • Title

    MTJ-Based State Retentive Flip-Flop With Enhanced-Scan Capability to Sustain Sudden Power Failure

  • Author

    Iyengar, Anirudh Srikant ; Ghosh, Swaroop ; Jae-Won Jang

  • Author_Institution
    Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
  • Volume
    62
  • Issue
    8
  • fYear
    2015
  • Firstpage
    2062
  • Lastpage
    2068
  • Abstract
    We present two non-volatile flip-flops (NVFFs) that incorporate magnetic tunnel junctions (MTJ) to ensure fast data storage and restoration from intentional and unintentional power outages. The proposed designs also facilitate enhanced scan mode testing capability by exploiting the nonvolatile latch to function as hold latch for delay testing. The proposed NVFF eliminates additional write drivers, and can operate at up to 2 GHz at 1.1 V, with 0.55 pJ of energy consumption in 22 nm predictive technology. We also address the issue of write asymmetry of MTJ through careful transistor upsizing to achieve near uniform write latency. A data-dependent power gating technique is proposed to mitigate the high static current during retention and back-to-back writing of the identical input data. The proposed gated NVFF achieves several orders of magnitude energy saving at the expense of 1.56X area compared to a standard enhanced scan flip-flop.
  • Keywords
    energy consumption; flip-flops; integrated circuit testing; logic design; low-power electronics; magnetic tunnelling; random-access storage; synchronisation; MTJ; NVFF; back-to-back writing; data storage; data-dependent power gating technique; delay testing; energy 0.55 pJ; energy consumption; hold latch; magnetic tunnel junctions; magnitude energy saving; nonvolatile flip-flops; nonvolatile latch; power failure; power outages; predictive technology; scan mode testing capability; size 22 nm; standard enhanced scan flip-flop; state retentive flip-flop; static current; voltage 1.1 V; write asymmetry; write drivers; write latency; Clocks; Delays; Inverters; Latches; Logic gates; Magnetization; Switches; Enhanced scan (ES); magnetic tunnel junction (MTJ); nonvolatile flip-flop (NVFF); power gating;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems I: Regular Papers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1549-8328
  • Type

    jour

  • DOI
    10.1109/TCSI.2015.2440738
  • Filename
    7166402