Title :
A Dynamically Reconfigurable Pixel Processor System Based on Power/Energy-Performance-Accuracy Optimization
Author :
Llamocca, Daniel ; Pattichis, Marios
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of New Mexico, Albuquerque, NM, USA
fDate :
3/1/2013 12:00:00 AM
Abstract :
We introduce a dynamically reconfigurable framework for implementing single-pixel operations. The system relies on a multiobjective optimization scheme that generates Pareto-optimal realizations in the power/energy-performance-accuracy (PPA/EPA) spaces. The Pareto-optimal realizations and their PPA/EPA values are stored in DDR-SDRAM and can be chosen dynamically to meet time-varying constraints. Results are shown in terms of power, accuracy (peak signal-to-noise ratio) of the resulting image, and performance in frames per second. Dynamic PPA/EPA management is implemented using dynamic partial reconfiguration and dynamic frequency control.
Keywords :
DRAM chips; SRAM chips; image processing; optimisation; DDR-SDRAM; Pareto-optimal realizations; dynamic PPA-EPA management; dynamic frequency control; dynamic partial reconfiguration; dynamically reconfigurable pixel processor system; multiobjective optimization scheme; peak signal-to-noise ratio; power-energy-performance-accuracy optimization; single-pixel operations; time-varying constraints; Accuracy; Clocks; Field programmable gate arrays; Frequency control; Hardware; Nickel; Table lookup; Dynamic partial reconfiguration (DPR); field-programmable gate-array (FPGA); look-up table (LUT)-based architectures;
Journal_Title :
Circuits and Systems for Video Technology, IEEE Transactions on
DOI :
10.1109/TCSVT.2012.2210664
