Investigation of Hysteresis Phenomenon in Floating-Gate NAND Flash Memory Cells

The origin of hysteresis phenomenon in floating-gate (FG) NAND flash memory cells in cell strings was identified. To analyze the hysteresis phenomenon in FG NAND flash memory strings, pulsed I-V and fast transient bitline current (I_BL) measurements were used in this study. It was found that the hysteresis phenomenon is originated by traps in the bottom oxide of the oxide/nitride/oxide interpoly dielectric. When the control-gate voltage (V_CG) of a selected cell in the erased state is 5 V, the electrons in the FG are captured in the traps, because the trap energy level (ET) is lower than the Fermi energy level (E_F) of the FG (E_T - E_F <; 0), which leads to the increase in I_BL. When the V_CG of the selected cell is V_th, trapped electrons are emitted to the FG, because the E_T is higher than the E_F of the FG (E_T - E_F > 0), which leads to the decrease in I_BL.