Two approaches to improve FPGA performance for the stereo camera of the Chang´E-1 satellite

This article outlines the design of the CCD Stereo Camera optical sensor on the Chang´E-1 (CE-1) satellite which was created for China´s first Lunar Exploration Program. The camera was designed to acquire three-dimensional stereoscopic images of the lunar surface based upon three-line array photogrammetric theory. A frame transfer CCD with 1024x1024 pixels is used to build a particular three-line array sensor. One of the main parts of this article is the design methodologies for the digital hardware readout circuits of the particular three-line array sensor using FPGA. At the beginning of the project, advanced high performance devices were not available, and the available FPGA was ACTEL´s anti-fuse type A1020B, which has limited speed performance and logical resources. The FPGA implementation therefore is supported by two novel approaches to resolve two problems due to the device limitations. The results of the on-board flight validate that the proposed methodologies were successful.