DocumentCode
739973
Title
Static Test Compaction for Low-Power Test Sets by Increasing the Switching Activity
Author
Pomeranz, Irith
Author_Institution
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Volume
23
Issue
9
fYear
2015
Firstpage
1936
Lastpage
1940
Abstract
This brief describes a static test compaction procedure for low-power test sets, which is based on the observation that a higher switching activity leads to a smaller number of tests. To use this observation in the context of low-power test sets, this brief makes the following new observations. First, considering the number of tests in a given test set where a line g makes a 0 → 1 or a 1 → 0 transition, there are large variations in this number between different lines. Increasing the switching activity only for a subset G of lines that make the smallest numbers of signal transitions is sufficient for achieving test compaction. Second, the switching activity for the subset G can be increased in a way that the specific values that the lines assume can occur during functional operation, and the maximum switching activity for the test set does not increase. These observations allow the compacted test set to remain a low-power test set. Experimental results demonstrate significant reductions in the numbers of tests in low-power test sets for transition faults in benchmark circuits.
Keywords
integrated circuit testing; low-power electronics; benchmark circuits; functional operation; low-power test sets; signal transitions; static test compaction; switching activity; transition faults; Benchmark testing; Circuit faults; Clocks; Compaction; Power dissipation; Switches; Very large scale integration; Broadside tests; low-power test sets; skewed-load tests; static test compaction; transition faults; transition faults.;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/TVLSI.2014.2345762
Filename
6880855
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