A Multiple-Stage Parallel Replica-Bitline Delay Addition Technique for Reducing Timing Variation of SRAM Sense Amplifiers

A multiple-stage parallel replica-bitline (RBL) delay addition technique for reducing the timing variation of static random access memory (SRAM) sense amplifiers (SAs) is proposed. Multiple-stage RBLs with a sufficient count of replica cells are utilized in parallel. Subsequently, the RBL delay of each stage is digitized and added together by the proposed timing addition circuit to the target timing for SAs. Compared with existing techniques, the proposed technique can achieve lower timing variation, which reduces the SRAM access time, particularly at a low supply voltage. At the supply voltage of 0.8 V, the simulation results show that the standard deviation of the SA-enable timing with the proposed technique is 80% smaller than that with a conventional RBL technique in Taiwan Semiconductor Manufacturing Company 65-nm CMOS technology. Therefore, the SRAM access time is reduced by 21% at 0.8-V supply voltage, whereas the area of 16-kb SRAM is increased by 3.5%.