• DocumentCode
    740109
  • Title

    Master–Slave Match Line Design for Low-Power Content-Addressable Memory

  • Author

    Yen-Jen Chang ; Tung-Chi Wu

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Nat. Chung Hsing Univ., Taichung, Taiwan
  • Volume
    23
  • Issue
    9
  • fYear
    2015
  • Firstpage
    1740
  • Lastpage
    1749
  • Abstract
    Content-addressable memory (CAM) is a hardware storage commonly used in the fast lookup applications. However, the parallel comparison feature costs the CAM memory large power consumption. In this paper, we propose a new CAM word architecture, called master-slave match line (MSML) design, which aims to combine the master-slave architecture and charge refill minimization technique to reduce the CAM power dissipated in the match lines (MLs). Unlike the conventional design, where only one single ML is used, our design uses one master-ML (MML) and several slave-MLs (SMLs) to perform the search operation. By sharing the MML charge with only the mismatched SML, our design can minimize the MML charge refill swing, such that the ML power consumption can be reduced effectively. Theoretically, the ML power saving is at least 50%, which is independent of the search pattern and match case. Compared with the conventional NOR-type CAM design, the simulation results show that the MSML design with the best configuration can reduce the ML energy consumption by range 7%-57%, which increases with the word size. In addition, we further propose a modified CAM cell to facilitate the MSML match performance, i.e., MSMLhp design, which can even result in 28% and 69% energy-delay product improvement compared with the original MSML and traditional CAM designs in the 128-bit word size case.
  • Keywords
    content-addressable storage; low-power electronics; CAM word architecture; charge refill minimization technique; hardware storage; low power content addressable memory; master-slave match line design; search operation; Capacitance; Computer aided manufacturing; Computer architecture; Discharges (electric); Microprocessors; Power demand; Transistors; Charge refill minimization; content-addressable memory (CAM); low-power; master–slave architecture; master???slave architecture; match line (ML);
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2014.2345512
  • Filename
    6881742