DocumentCode
740127
Title
Correction to “A 2 Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60 GHz Short-Range Wireless Communication”
Author
Mitomo, Toshiya ; Tsutsumi, Yukako ; Hoshino, Hiroaki ; Hosoya, M. ; Wang, Tao ; Tsubouchi, T. ; Tachibana, Ryoichi ; Sai, Akihide ; Kobayashi, Yoshiyuki ; Kurose, Daisuke ; Ito, Takao ; Ban, Koichiro ; Tandai, Tomoya ; Tomizawa, Takeshi
Author_Institution
Wireless System Laboratory Corporate Reserch & Development Center, Toshiba Corporation, Japan
Volume
48
Issue
6
fYear
2013
fDate
6/1/2013 12:00:00 AM
Firstpage
1540
Lastpage
1540
Abstract
The authors made an error in Fig. 19 in the above-named article [ibid., vol. 47, no. 12, pp. 3160–3171, Dec. 2012]. The figure is the same as Fig. 13 by mistake. The correct figure "Data rate/throughput measurement setup" is shown here. The authors apologize for any confusion.
Keywords
Antennas; CMOS integrated circuits; Indium tin oxide; Solid state circuits; Throughput; Transceivers; Wireless communication;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.2013.2253424
Filename
6509982
Link To Document