150–850 MHz High-Linearity Sine-wave Synthesizer Architecture Based on FIR Filter Approach and SFDR Optimization

A low distortion sinusoidal waveform synthesizer architecture is proposed. The synthesizer utilizes 50% duty cycle and differential-mode circuitry to eliminate the even order harmonics, and it also implements a 5-phase 3-amplitude harmonic cancellation technique to suppress the 3rd, 5th, 7th, and 9th order harmonics. The compact system architecture consists of a 12-phase ring oscillator, a weighted resistor summing network, and an RC output filter. Phase shifters are adopted in the ring oscillator to enable the control of an external harmonic cancellation optimization algorithm. The proposed application of the optimization algorithm compensates the errors in the circuit and further improves the linearity of the output waveforms. This synthesizer is fabricated in 180 nm standard CMOS technology, occupies a 0.08 mm² silicon area and achieves the spur-free dynamic range (SFDR) of 59 to 70 dBc from 150 to 850 MHz after the optimization procedure. It can operate from a 1 to 1.8 V supply voltage and achieve a power consumption from 9.11 to 57 mW.