DocumentCode :
741496
Title :
A New Accelerated Endurance Test for Terabit NAND Flash Memory Using Interference Effect
Author :
Jaewon Cha ; Wooheon Kang ; Junsub Chung ; Kunwoo Park ; Sungho Kang
Author_Institution :
Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea
Volume :
28
Issue :
3
fYear :
2015
Firstpage :
399
Lastpage :
407
Abstract :
Limited endurance of E/W cycles is a unique restriction of flash memories and the endurance characteristics usually take a longer time to test. In this paper, we proposed a novel endurance test scheme that takes advantage of the parasitic cell-to-cell interference as well as a shortened program time to accelerate the endurance test for terabit NAND flash memory. The novelty of the new scheme is the use of a new test sequence known as even/odd row address sequence (EORAS). The interference effect during the program operation mainly affects the threshold voltage widening in the victim cell and leads to errors linearly during the read operation. We mainly focus on the correlation between the interference and device error rate during the endurance test. Based on the correlation, we use the interference effect as an acceleration factor in EORAS. EORAS is composed of a new program operation for unit test-time reduction. Our experimental results show that the proposed scheme method can induce the raw bit error rate by 50% and thereby improve the cycling time by 19.4% in a 3×-nm flash device. The proposed scheme method can also induce the raw bit error rate by 80% and thereby improve the endurance test time by 30.8% in a 2×-nm flash device. Consequently, the new endurance scheme reduces the test time by 68.4%.
Keywords :
NAND circuits; error statistics; flash memories; integrated circuit testing; interference; life testing; E/W cycle; EORAS; accelerated endurance test; bit error rate; cycling time; device error rate; even/odd row address sequence; parasitic cell-to-cell interference effect; terabit NAND flash memory; test-time reduction; threshold voltage; Bit error rate; Flash memories; Interference; Latches; Life estimation; Performance evaluation; NAND flash memory; Test time reduction; acceleration test; erase/write (E/W) cycling; erase/write cycling; multi-level cell; multilevel cell; reliability testing; test time reduction;
fLanguage :
English
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
Publisher :
ieee
ISSN :
0894-6507
Type :
jour
DOI :
10.1109/TSM.2015.2429211
Filename :
7101285
Link To Document :
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