• DocumentCode
    741986
  • Title

    Functionality-Enhanced Logic Gate Design Enabled by Symmetrical Reconfigurable Silicon Nanowire Transistors

  • Author

    Trommer, Jens ; Heinzig, Andre ; Baldauf, Tim ; Slesazeck, Stefan ; Mikolajick, Thomas ; Weber, Walter M.

  • Author_Institution
    Namlab gGmbH, Dresden, Germany
  • Volume
    14
  • Issue
    4
  • fYear
    2015
  • fDate
    7/1/2015 12:00:00 AM
  • Firstpage
    689
  • Lastpage
    698
  • Abstract
    Reconfigurable silicon nanowire field-effect transistors (RFETs) combine the functionality of classical unipolar p-type and n-type FETs in one universal device. In this paper, we show devices exhibiting full symmetry between pand n-functionality, while having identical geometry. Scaling trends and feasibility for digital circuit integration are evaluated based on TCAD simulations. The method of logical effort is applied to analyze fundamental differences in circuit topology using this unique type of multigate transistors. We introduce a set of multifunctional logic gates based on RFETs providing all basic Boolean functions, including NAND/NOR, AND/OR, and XOR/XNOR, and compared them with classical implementations. Two 1-bit full adders based on those gates are presented as an insightful example that RFETs are one possible solution to increase the system functionality. Moreover, it is shown that an asymmetric transistor layout with individual optimization of both top gates can be used to increase the speed of those circuits.
  • Keywords
    Boolean functions; adders; elemental semiconductors; field effect transistors; integrated circuit layout; integrated logic circuits; logic gates; nanoelectronics; nanowires; network topology; optimisation; semiconductor device models; silicon; technology CAD (electronics); 1-bit full adders; AND/OR function; Boolean functions; NAND/NOR function; RFET; Si; TCAD simulations; XOR/XNOR function; asymmetric transistor layout; circuit topology; classical unipolar n-type FET; classical unipolar p-type FET; digital circuit integration; functionality-enhanced logic gate design; multifunctional logic gates; multigate transistors; optimization; symmetrical reconfigurable silicon nanowire transistors; Capacitance; Delays; Inverters; Logic gates; Performance evaluation; Silicon; Transistors; Ambipolar transistors; RFET; Schottky field effect transistors; ambipolar transistors; device-circuit co-optimization; functional enhancement; logic gates; logical effort; multigate; polarity control; reconfigurable transistor; schottky field effect transistors; silicon nanowires;
  • fLanguage
    English
  • Journal_Title
    Nanotechnology, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1536-125X
  • Type

    jour

  • DOI
    10.1109/TNANO.2015.2429893
  • Filename
    7104145