Modeling of Jitter in Bang-Bang CDR With Fourier Series Analysis

Bang-bang clock and data recovery (BBCDR) circuits are hard nonlinear systems due to the nonlinearity introduced by the binary phase detector (BPD). In this paper, jitter transfer and jitter tolerance of the second-order BBCDR are characterized by the Fourier series analysis and formulating the time domain waveforms. As a result, a new equation is presented to obtain corner frequency. Also, the jitter tolerance is expressed in a closed form as a function of loop parameters. The presented method is general enough to be used for designing the BBCDR. System level simulation is used to validate the analytical results with particular emphasis on jitter transfer and tolerance characteristics. The experiments all show excellent conformance between analytical equations and simulation results.