Title :
A Two-Dimensional Gate Threshold Voltage Model for a Heterojunction SOI-Tunnel FET With Oxide/Source Overlap
Author :
Chander, Sweta ; Baishya, Srimanta
Author_Institution :
Dept. of Electron. & Commun. Eng., Nat. Inst. of Technol. Silchar, Silchar, India
fDate :
7/1/2015 12:00:00 AM
Abstract :
A two-dimensional (2D) analytical gate threshold voltage model for a heterojunction silicon-on-insulator tunnel field-effect transistor structure with gate oxide overlap is developed. The infinite series method, with suitable boundary conditions, is used to solve the 2D Poisson´s equation for surface potential. The surface potential is used to develop the expression for the proposed analytical threshold voltage in closed form. Developed threshold voltage is verified for different gate length, drain voltage, oxide thickness, and gate dielectric materials against Synopsys Technology Computer-Aided Design numerical simulation results and found to predict the simulated results accurately.
Keywords :
Poisson equation; dielectric materials; high electron mobility transistors; numerical analysis; semiconductor device models; series (mathematics); silicon-on-insulator; 2D Poisson equation; 2D analytical gate threshold voltage model; Si; Synopsys Technology Computer-Aided Design; drain voltage; gate dielectric materials; gate length; heterojunction SOI-tunnel FET; heterojunction silicon-on-insulator tunnel field-effect transistor; infinite series method; oxide thickness; oxide-source overlap; surface potential; Analytical models; Dielectric materials; Logic gates; Mathematical model; Numerical models; Semiconductor process modeling; Threshold voltage; Band-to-Band Tunneling; Silicon on Insulator (SOI); Subthreshold Swing; Threshold Voltage; Threshold voltage; Tunnel FET; band-to-band tunneling; silicon on insulator (SOI); subthreshold swing; tunnel FET;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2015.2432061
