Title :
Statistical Run-Time Verification of Analog Circuits in Presence of Noise and Process Variation
Author :
Narayanan, Rajesh ; Seghaier, Ibtissem ; Zaki, Mohamed H. ; Tahar, Sofiene
Author_Institution :
Dept. of Electr. & Comput. Eng., State Univ. of New York, New Paltz, NY, USA
Abstract :
Noise and process variation present a practical limit on the performance of analog circuits. This paper proposes a methodology for modeling and verification of analog designs in the presence of shot noise, thermal noise, and process variations. The idea is to use stochastic differential equations to model noise in additive and multiplicative form and then combine process variation due to 0.18 μm technology in a statistical run-time verification environment. The efficiency of Monte-Carlo and Bootstrap statistical techniques are compared for a Colpitts oscillator and a phase locked loop-based frequency synthesizer circuit.
Keywords :
Monte Carlo methods; adders; analogue integrated circuits; differential equations; integrated circuit design; integrated circuit modelling; integrated circuit noise; integrated circuit reliability; multiplying circuits; oscillators; phase locked loops; shot noise; stochastic processes; thermal noise; Colpitts oscillator; Monte-Carlo technique; additive form; analog circuits performance; analog design modeling; analog design verification; bootstrap statistical techniques; multiplicative form; noise model; phase locked loop-based frequency synthesizer circuit; process variation; shot noise; size 0.18 mum; statistical run-time verification environment; stochastic differential equations; thermal noise; Analog circuits; Mathematical model; Monitoring; Noise; Numerical models; Stochastic processes; Testing; Analog designs; noise; process variation; run-time verification; statistical techniques; stochastic differential equations;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2012.2219083
