Title :
An Integrator-Based Pipelined ADC With Digital Calibration
Author :
Dong Wang ; Keane, John P. ; Hurst, Paul J. ; Lewis, Stephen H.
Author_Institution :
Univ. of California Davis, Davis, CA, USA
Abstract :
A 12-bit pipelined analog-to-digital converter (ADC) uses a first-stage integrator-based open-loop residue amplifier and integrator nonlinearities are foreground calibrated. In the remaining traditional closed-loop stages, gain errors and memory errors are background calibrated. Separate reference voltages are used in the first three ADC stages to reduce interstage coupling. A 0.25-μm CMOS prototype dissipates 140 mW and occupies an active area of 5 mm2. At 40 megasamples/s (40 MS/s), the calibration improves the spurious-free dynamic range from 51.2 to 95.1 dB and the signal-to-noise-plus-distortion ratio from 43.7 to 69.0 dB.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; calibration; reference circuits; CMOS prototype; analog-to-digital converter; digital calibration; first-stage integrator-based open-loop residue amplifier; gain errors; integrator nonlinearities; integrator-based pipelined ADC; interstage coupling; memory errors; power 140 mW; reference voltages; size 0.25 mum; CMOS integrated circuits; Calibration; Gain; Jitter; Prototypes; Solid state circuits; Adaptive calibration; CMOS analog integrated circuits; Data conversion; complementary metal???oxide???semiconductor (CMOS) analog integrated circuits; data conversion;
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2015.2435514
